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1. general description the em783-sc/sp/tp/mc3/mc6 is an arm cortex -m0-based, low-cost 32-bit family of application processors, designed for energy measurement and monitoring applications. the em783 offers programmab ility and on-chip metrology fu nctionality combined with a low power, simple instructio n set. it also has memory addressing together with reduced code size compared to existing 8/16-bit architectures. the em783 operate at cpu frequencies of up to 48 mhz. the digital peripherals on the em783 include: ? 32 kb of flash memory ? 4 kb of eeprom data memory ? 8 kb of sram data memory ? fast-mode plus i 2 c-bus interface ? rs-485/eia-485 usart ? one ssp controller ? two general-purpose counter/timers ? up to 22 general-purpose i/o pins a metrology engine with built-in temperature sensor is used for energy measurements. a 10-bit dac and an internal voltage reference are also available. 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 48 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug (swd). ? system tick timer. ? memory: ? 32 kb on-chip flash program memory. ? 4 kb on-chip eeprom data memory fo r energy register s and calibration parameters; byte erasable and byte programmable. ? 8 kb sram data memory. ? 16 kb boot rom. ? in-system programming (isp) for flash and in-application programming (iap) for flash and eeprom via on-chip bootloader software. ? includes rom-based 32-bit integer division routines. em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom rev. 2 ? 17 january 2014 product data sheet
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 2 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? digital peripherals: ? up to 22 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. ? up to 9 pins are configurable with a digita l input glitch filter for removing glitches with widths of 10 ns. two pi ns are configurable for 20ns glitch filter and another two pins are configurable for 50 ns glitch filters. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current source output driver (20 ma) on one pin (p0_21). ? high-current sink driver (20 ma) on true open-drain pins (p0_2 and p0_3). ? two general-purpose counter/timers with a total of up to four capture inputs and five match outputs. ? programmable windowed watchdog timer (wwdt) with a dedicated, internal low-power watchdog oscillator (wdosc). ? analog peripherals: ? metrology engine for smart metering with one voltage input, one bias input, from two up to six current inputs and a temperature sensor. ? internal voltage reference. ? 10-bit dac with flexible conversion triggering. ? serial interfaces: ? usart with fractional baud rate gener ation, internal fifo, support for rs-485/9-bit mode and synchronous mode. ? one ssp controller with fifo and multi-protocol capabilities. ? i 2 c-bus interface supporting the full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address recognition and monitor mode. ? clock generation: ? crystal oscillator (sysosc) with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillator (irc) trimm ed to 1 % accuracy that can optionally be used as a system clock. ? internal low-power, low-frequency os cillator (lfosc) with programmable frequency output. ? clock input for external syste m clock (25 mhz typical). ? pll allows cpu operation up to the maxi mum cpu rate with the irc, the external clock, or the sysosc as clock sources. ? clock output function with divider that ca n reflect the sysosc, the irc, the main clock, or the lfosc. ? power control: ? supports arm cortex-m0 sleep mode as reduced power mode. ? power profiles residing in boot rom allowed to optimize performance and minimize power consumption for any given application through one simple function call. ? processor wake-up from reduced power mode using any interrupt. ? power-on reset (por). ? brownout detect (bod) with two separate programmable thresholds for interrupt and one hardware controlled reset trip point. ? por and bod are always enabled for rapid uvlo protection against power supply voltage drops below 2.4 v. ? unique device serial number for identification.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 3 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? single 3.3 v power supply (2.6 v to 3.6 v). ? temperature range ? 40 ? c to +85 ? c. ? available as a 33-pin hvqfn 7 mm ? 7 mm ? 0.85 mm package. 3. applications ? smart plugs and plug meters ? single phase residential meters ? industrial submeters ? server power monitoring ? smart appliances 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version em783-sc hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a em783-sp hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a em783-tp hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a EM783-MC3 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a em783-mc6 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a table 2. ordering options type number flash sram eeprom metrology engine inputs 10-bit dac usart ssp/ spi i 2 c package em783-sc 32 kb 8 kb 4 kb 1x i, 1x v 1 1 1 1 hvqfn33 em783-sp 32 kb 8 kb 4 kb 2x i, 1x v 1 1 1 1 hvqfn33 em783-tp 32 kb 8 kb 4 kb 3x i, 3x v 1 1 1 1 hvqfn33 EM783-MC3 32 kb 8 kb 4 kb 3x i, 1x v 1 1 1 1 hvqfn33 em783-mc6 32 kb 8 kb 4 kb 6x i, 1x v 1 1 1 1 hvqfn33
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 4 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 5. block diagram fig 1. em783 block diagram sram 8 kb arm cortex-m0 test/debug interface flash 32 kb eeprom 4 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions reset clocks, internal voltage reference, and controls swd em783 aaa-007681 slave slave slave rom 16 kb slave slave ahb-lite bus gpio ports clkout clkin irc, lfosc, wdosc sysosc por bod usart 32-bit counter/timer 0 ix ix_l ix_h vx vbias aout rxd txd rts cts sclk pmu system control windowed watchdog timer gpio interrupts gpio group0/1 interrupt 16-bit counter/timer 0 ct32b0_mat[2:0] ct32b0_cap[2, 0] ct16b0_mat[2:1] ct16b0_cap[1:0] gpio pins gpio pins 10-bit dac system bus ssp0 sck0, ssel0, miso0, mosi0 i 2 c-bus ioconfig scl, sda (2) (1) open-drain pins (2) standard i/o pins scl, sda (2) scl, sda (1) scl, sda (2) xtalin xtalout metrology engine
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 5 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 6. pinning information 6.1 pinning 6.2 pin description all functional pins on the em783, except fo r metrology inputs, are mapped to gpio port 0 (see ta b l e 3 ). the port pins are multiplexed to a ccommodate more than one function (see ta b l e 4 ). the ioconfig register, contro ls the pin function (see the em783 user manual ). the standard i/o pad configur ation is illustrated in figure 24 and a detailed pin description is given in table 4 . fig 2. pin configuration hvqfn33 package aaa-007680 transparent top view 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss table 3. pin multiplexing function type port glitch filter pin system clocks, reset, and wake-up clkin i p0_1 no 3 p0_12 no 31 p0_19 no 9 p0_24 no 7 clkout o p0_1 no 3 p0_19 no 9 xtalin i (analog) - - 4 xtalout o (analog) - - 5 reset i p0_0 20 ns [1] 2 serial wire debug (swd) swclk i p0_2 50 ns [2] 10 p0_5 10 ns [2] 19
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 6 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom swdio i/o p0_3 50 ns [2] 11 p0_10 10 ns [2] 25 metrology engine v1 i (analog) - no 28 vbias i (analog) - no 14 v1 i (analog) - no 22 vbias i (analog) - no 23 i1 i (analog) - no 20 i1_l i (analog) - no 20 i1_h i (analog) - no 21 i5 i (analog) - no 21 i2_l i (analog) - no 24 i2 i (analog) - no 24 i2_h i (analog) - no 25 v2 i (analog) - no 25 i6 i (analog) - no 25 i3_l i (analog) - no 26 i3 i (analog) - no 26 i3_h i (analog) - no 27 i4 i (analog) - no 27 v3 i (analog) - no 27 analog peripherals aout o (analog) p0_4 no 18 atrg0 i (analog) p0_16 10 ns [2] 13 i 2 c-bus interface scl i/o p0_2 50 ns [2] 10 p0_12 no 31 p0_16 10 ns [2] 13 p0_24 no 7 sda i/o p0_3 50 ns [2] 11 p0_13 10 ns [2] 32 p0_15 10 ns [2] 27 p0_25 no 12 ssp0 controller miso0 i/o p0_22 10 ns [2] 17 mosi0 i/o p0_4 10 ns [2] 18 p0_19 no 9 sck0 i/o p0_5 10 ns [2] 19 p0_20 no 15 table 3. pin multiplexing ?continued function type port glitch filter pin
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 7 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] always on. [2] programmable on/off. by default, the glitch filter is disabled. ssel0 i/o p0_1 no 3 p0_18 no 8 usart rxd i p0_1 no 3 p0_12 no 31 txd o p0_13 no 32 p0_15 no 27 p0_26 no 1 sclk i/o p0_11 10 ns [2] 26 p0_21 no 16 p0_23 no 30 cts i p0_9 10 ns [2] 24 p0_21 no 16 rts o p0_10 no 25 p0_23 no 30 16-bit counte r/timer ct16b0 ct16b0_cap0 i p0_2 50 ns [2] 10 p0_18 no 8 ct16b0_cap1 i p0_16 10 ns [2] 13 ct16b0_mat1 o p0_4 no 18 p0_9 no 24 ct16b0_mat2 o p0_5 no 19 p0_10 no 25 32-bit counte r/timer ct32b0 ct32b0_cap0 i p0_11 10 ns [2] 26 p0_23 no 30 ct32b0_cap2 i p0_15 10 ns [2] 27 p0_26 no 1 ct32b0_mat0 o p0_12 no 31 ct32b0_mat1 o p0_13 no 32 ct32b0_mat2 o p0_1 no 3 supply and ground pins v dd(io) supply - - 6 v dd(3v3) supply - - 29 v ss ground - - 33 v ss(io) ground - - 33 table 3. pin multiplexing ?continued function type port glitch filter pin
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 8 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ta b l e 4 shows all pins in order of increasing pin number. the default function after reset is listed first. port pins p0_0 to p0_26 have inte rnal pull-up resistors enabled after reset except for the true open-drain pins p0_2 and p0_3. pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the ioconfig registers for each of the port pins. table 4. em783 pin description pin no. em783 symbol type reset state [1] description sc sp tp mc3 mc6 1 p0_26/txd/ct32b0_cap2 [2] i/o i; pu p0_26 ? general-purpose digital input/output pin. o- txd ? transmitter data output for usart. i- ct32b0_cap2 ? capture input 2 for 32-bit timer 0. 2 reset /p0_0 [3] ii; pu reset ? external reset input with fixed 20 ns glitch filter: a low going pulse on this pin resets the device. it causes i/o ports and peripherals to take on their default states and processor execution to begin at address 0. i/o - p0_0 ? general-purpose digital input/output pin. 3 p0_1/rxd/clkout/ct32b0_ mat2/ssel0/clkin [2] i/o i; pu p0_1 ? general-purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. i- rxd ? receiver data input for usart. o- clkout ? clock output. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. i/o - ssel0 ? slave select for ssp0. i- clkin ? external clock input. 4xtalin [4] - - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. 5xtalout [4] - - output from the o scillator amplifier. 6v dd(io) [5] [6] - - 3.3 v input/output supply voltage. 7 p0_24/scl/clkin [2] i/o i; pu p0_24 ? general-purpose digital input/output pin. i/o - scl ? i 2 c-bus clock input/output. this pin is not an i 2 c-bus open-drain pin [10] . i- clkin ? external clock input. 8 p0_18/ssel0/ct16b0_cap0 [2] i/o i; pu p0_18 ? general-purpose digital input/output pin. i/o - ssel0 ? slave select for ssp0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. 9 p0_19/clkin/clkout/mosi0 [2] i/o i; pu p0_19 ? general-purpose digital input/output pin. i- clkin ? external clock input. o- clkout ? clock output. i/o - mosi0 ? master out slave in for ssp0.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 9 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 10 p0_2/scl/swclk/ct16b0_cap0 [7] i/o i; ia p0_2 ? general-purpose digital input/output pin. high-current sink (20 ma) or standard-current sink (4 ma) programmable; true open-drain for all pin functions. input glitch filter (50 ns) capable. i/o - scl ? i 2 c-bus clock (true open- drain) input/output with selectable 50 ns input glitch filter. input glitch filter (50 ns) capable. i- swclk ? serial wire debug clock (secondary). input glitch filter (50 ns) capable. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. 11 p0_3/sda/swdio [7] i/o i; ia p0_3 ? general-purpose digital input/output pin. high-current sink (20 ma) or standard-current sink (4 ma) programmable; true open-drain for all pin functions. input glitch filter (50 ns) capable. i/o - sda ? i 2 c-bus data (true open-drain) input/output. input glitch filter (50 ns) capable. i/o - swdio ? serial wire debug i/o (secondary). input glitch filter (50 ns) capable. 12 p0_25/sda [2] i/o i; pu p0_25 ? general-purpose digital input/output pin. i/o - sda ? i 2 c-bus data input/output. this pin is not an i 2 c-bus open-drain pin [10] . 13 p0_16/atrg0/ct16b0_cap1/scl [8] i/o i; pu p0_16 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. i- atrg0 ? conversion trigger for dac. input glitch filter (10 ns) capable. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. input glitch filter (10 ns) capable. i/o - scl ? i 2 c-bus clock input/output. this pin is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. 14 vbias [8] i- vbias ? bias voltage input for metrology engine. 15 p0_20/sck0 [2] i/o i; pu p0_20 ? general-purpose digital input/output pin. i/o - sck0 ? serial clock for ssp0. 16 p0_21/cts /sclk [2] i/o i; pu p0_21 ? general-purpose digital input/output pin. if configured as output, this pin is a high-current source output driver (20 ma). i- cts ? clear to send input for usart. i/o - sclk ? serial clock for usart. 17 p0_22/miso0 [2] i/o i; pu p0_22 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - miso0 ? master in slave out for ssp0. input glitch filter (10 ns) capable. table 4. em783 pin description ?continued pin no. em783 symbol type reset state [1] description sc sp tp mc3 mc6
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 10 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 18 p0_4/aout/ct16b0_mat1/mosi0 [9] i/o i; pu p0_4 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- aout ? dac output. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. i/o - mosi0 ? master out slave in for ssp0. input glitch filter (10 ns) capable. 19 swclk/p0_5/ct16b0_mat2/sck0 [8] ii; pu swclk ? primary (default) serial wire debug clock. input glitch filter (10 ns) capable. i/o - p0_5 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i/o - sck0 ? serial clock for ssp0. input glitch filter (10 ns) capable. 20 i1_l i1_l i1 i1_l i1 [9] i- i1_l ? low-gain current input for metrology engine of sc, sp and mc3 variant. i- i1 ? current input for metrology engine of tp and mc6 variants. 21 i1_h i1_h r i1_h i5 [8] i- i1_h ? high-gain current input for metrology engine of sc, sp and mc3 variant. i- i5 ? current input for metrology engine of mc6 variant. ii; pu r ? reserved 22 v1 [8] i- v1 ? voltage input for metrology engine. 23 vbias [8] i- vbias ? bias voltage input for metrology engine. 24 r/p0_9/ ct16b0_ mat1/cts i2_l i2 i2_l i2 [8] ii; pu r ? reserved i/o - p0_9 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. i- cts ? clear to send input for usart. input glitch filter (10 ns) capable. i- i2_l ? low-gain current input for metrology engine of sp and mc3 variant. i- i2 ? current input for metrology engine of tp and mc6 variants. table 4. em783 pin description ?continued pin no. em783 symbol type reset state [1] description sc sp tp mc3 mc6
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 11 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 25 swdio/p0_10/ ct16b0mat2/ rts i2_h v2 i2_h i6 [8] i/o i; pu swdio ? primary (default) serial wire debug i/o. input glitch filter (10 ns) capable. i/o - p0_10 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. o- rts ? request to send output for usart. i- i2_h ? high-gain current input for metrology engine of sp and mc3 variant. i- i6 ? current input for metrology engine of mc6 variant. i- v2 ? voltage input for metrology engine of tp variant. 26 p0_11/sclk/ct32b0_ cap0 i3 i3_l i3 [8] i/o i; pu p0_11 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - sclk ? serial clock for usart. input glitch filter (10 ns) capable. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. input glitch filter (10 ns) capable. i- i3_l ? low-gain current input for metrology engine of mc3 variant. i- i3 ? current input for metrology engine of tp and mc6 variants. 27 p0_15/txd/ct32b0_c ap2/sda v3 i3_h i4 [8] i/o i; pu p0_15 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- txd ? transmitter data output for usart. i- ct32b0_cap2 ? capture input 2 for 32-bit timer 0. input glitch filter (10 ns) capable. i/o - sda ? i 2 c-bus data input/output. this pin is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. i- i3_h ? high-gain current input for metrology engine of mc3 variant. i- i4 ? current input for metrology engine of mc6 variant. i- v3 ? voltage input for metrology engine of tp variant. 28 v1 [2] i- v1 ? voltage input for metrology engine. 29 v dd(3v3) [5] [6] - - 3.3 v supply voltage to the metrology engine, internal regulator, and internal clock generator circuits. also used as the metrology engine reference voltage. 30 p0_23/rts /ct32b0_cap0/sclk [2] i/o i; pu p0_23 ? general-purpose digital input/output pin. o- rts ? request to send output for usart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. i/o - sclk ? serial clock for usart. table 4. em783 pin description ?continued pin no. em783 symbol type reset state [1] description sc sp tp mc3 mc6
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 12 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] pin state at reset for default function: i = input; o = out put; pu = internal pull-up resistor (weak pmos device) enabled; i a = inactive, no pull-up/down enabled. [2] 5 v tolerant pin providing standard digital i/o functions with configurable modes an d configurable hysteresis ( figure 24 ). [3] see figure 25 for the reset configuration. [4] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibility to noise). xtalout should be left floating. see section 12.1 if an external clock is connected to the xtalin pin. [5] if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the power supply pins are filtered for noise. using separate filtered supplies reduces the noise to the metr ology engine and analog blocks (see also section 12.1 ). [6] if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference betw een both supplies is smaller than or equal to 0.5 v. [7] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [8] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog i/o. when configured as an analog i/o, digital section of the pi n is disabled, and the pin is not 5 v tolerant ( figure 24 ). [9] not a 5 v tolerant pin due to special analog functionality. pi n provides standard digital i/o functions with configurable mo des, configurable hysteresis, and analog i/o. w hen configured as an analog i/o, the digi tal section of the pin is disabled ( figure 24 ). [10] i 2 c-bus pins are standard digital i/o pins and have limited perform ance and electrical characterist ics compared to the full i 2 c-bus specification. pins can be configured with an on-chip pull-up resistor (pmos device) and with open-drain mode. in this mode, ty pical bit rates of up to 100 kbit/s with 20 pf load are supported if t he internal pull-ups are enabled. higher bit rates can be achieved with an external resistor. [11] thermal pad. connect to ground. 31 p0_12/rxd/ct32b0_mat0/scl/clkin [2] i/o i; pu p0_12 ? general-purpose digital input/output pin. i- rxd ? receiver data input for usart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. i/o - scl ? i 2 c-bus clock input/output. this pin is not an i 2 c-bus open-drain pin [10] . i- clkin ? external clock input. 32 p0_13/txd/ct32b0_mat1/sda [8] i/o i; pu p0_13 ? general-purpose digital input/output pin. input glitch filter (10 ns) capable. o- txd ? transmitter data output for usart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. i/o - sda ? i 2 c-bus data input/output. this pin is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. 33 v ss(io) /v ss - - ground [11] . table 4. em783 pin description ?continued pin no. em783 symbol type reset state [1] description sc sp tp mc3 mc6
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 13 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 on-chip flash program memory the em783 contains up to 32 kb of on-chip flash program memory. 7.3 on-chip eeprom data memory the em783 contains up to 4 kb of on-chip eeprom data memory. remark: the top 64 bytes of the 4 kb eeprom ar e reserved and cann ot be written to. 7.4 on-chip sram the em783 contain a total of 8 kb, 4 kb, or 2 kb on-chip static ram data memory. 7.5 memory map the em783 incorporate several distinct memory regions, shown in the following figures. figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 512 kb in size and is divided to allow fo r up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this space allows simplifying the address decoding for each peripheral.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 14 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.6 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.6.1 features ? controls system exceptions and peripheral interrupts. ? in the em783, the nvic supports 32 vectored in terrupts including up to 8 inputs to the start logic from the individual gpio pins. fig 3. em783 memory map apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 usart pmu i 2 c-bus 11 - 13 reserved dac ssp0 reserved reserved reserved reserved reserved gpio interrupts gpio group0 int reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 0x4002 c000 10 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved reserved apb peripherals gpio 0x1000 0000 0x1000 2000 8 kb sram em783 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors aaa-007682 reserved reserved 16-bit counter/timer 0 ioconfig system control 0x4005 0000 0x4005 4000 22 0x4006 0000 23 gpio group1 int 0x4006 4000 24 21 19 20 flash/eeprom controller 0x0000 8000 32 kb on-chip flash 0xe000 0000 0xe010 0000 private peripheral bus
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 15 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interr upt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. up to eight gpio pins can be programmed to generate an interrupt for a level, and/or a rising edge, and/or a falling edge. the interrupt generating gpios ca n be selected from the gpio pins with a configurable input glitch filter. the interrupts can be generated regardless of the selected function. 7.7 ioconfig block the ioconfig block allows sele cted pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the approp riate pins before being activated and prior to any related interrupts being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. up to 9 pins can be configured with a digital i nput glitch filter for re moving voltage glitches with widths of 10 ns (see ta b l e 3 and table 4 ). two pins can be configured with a 20 ns input glitch filter. another two pins can be conf igured with a 50 ns digital input glitch filter. 7.8 fast general-purpose parallel i/o the gpio registers control the device pins th at are not connected to a specific peripheral function. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. em783 use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? an entire port value can be written in one instruction. gpio pins providing a digital function (maximum 22 pins), can be programmed to generate an interrupt for a level, and/or a rising ed ge, and/or a falling edge. 7.8.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with internal pull-up resistors enabled after reset, except for the i 2 c-bus true open-drain pins p0_2 and p0_3. ? pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the ioconfig block for each gpio pin. for the functional diagrams, see figure 24 and figure 25 .
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 16 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? control of the digital output slew rate allo wing to switch more ou tputs simultaneously without degrading the power/gro und distribution of the device. 7.9 usart the em783 contains one usart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the usart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.9.1 features ? maximum usart data bit rate of 3.125 mbit/s. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? supports a full modem control handshake interface. ? support for synchronous mode. 7.10 ssp serial i/o controller the em783 contains one ssp controller. the ssp controller can operate on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bu s during a given data transfer. the ssp supports full-duplex transfers, with frames of 4 bit s to 16 bits of data. the data flows from the master to the slave and from the slave to the master. in prac tice, often only one of the data-flows carries meaningful data. 7.10.1 features ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in spi mode). ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? 4-bit to 16-bit frame.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 17 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.11 i 2 c-bus serial i/o controller the em783 contains one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). a unique address recognizes each device which can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus that can be controlled by more than one bus master connected to it. 7.11.1 features ? the i 2 c-interface is a standard i 2 c-bus compliant interfac e with open-drain pins (p0_2 and p0_3). the i 2 c-bus interface also supports fast-mode plus with bit rates up to 1 mbit/s. ? the true open-drain pins p0_2 and p0_3 can be configured with a 50 ns digital input glitch filter. ? if the true open-drain pins are used for other purposes, a limited-performance i 2 c-bus interface can be configured from a choice of six gpio pins. the six gpio pins are configured in open-drain mode and with a pull-up resistor. in this mode, typical bit rates of up to 100 kbit/s with 20 pf load are supported if the internal pull-ups are enabled. higher bit rates can be achi eved with an external resistor. ? easy to configure as master, slave, or master/slave. ? fail-safe operation. when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c-bus are floating and do not disturb the bus. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.12 metrology engine the em783 contains a metrology engine design ed to collect voltage and current inputs. it uses these inputs to calculate the active power, reactive power, apparent power and power factor of a load. the purpose of the metrology engi ne is for billing and non-billing applications such as plug meters, smart a ppliances, industrial and consumer submeters.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 18 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.12.1 features ? up to 1.0 % accurate for scalable input so urces. it maintains this accuracy with a factor of 1 to 1000 down from the maximum current. ? automatically calculates: ? vrms ? irms ? active power in w ? reactive power in var ? apparent power in va ? power factor ? fundamental reactive power in var ? fundamental apparent power in va ? fundamental power factor ? non-fundamental apparent power ? non-active power ? total harmonic distortion of the current ? mains frequency ? cpu core temperature ? standard api for initializing, starting, stopping and reading data from the metrology engine using the arm cortex-m0. ? temperature measurement supporting temperature compensation. the temperature sensor has a maximum error of ? 3 degrees ? c over the ambient temperature range of ? 40 ? c to +85 ? c. ? very accurate mains frequency measurement. ? mains frequency operating range of 45 hz to 65 hz. ? eeprom can be used for energy registers and calibration parameters. ? measurements and active power according to iec 62053-21. 7.13 10-bit dac the dac allows generation of a variable, rail-to-rail analog output. 7.13.1 features ? 10-bit dac. ? resistor string architecture. ? buffered output. ? power-down mode. ? conversion speed controlled via a programmable bias current. ? optional output update modes: ? write operations to the dac register.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 19 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? a transition of pin atrg0. input signal must be held for a minimum of three system clock periods. ? a timer match signal. ? if the dac is not powered down, it hold s the output value during sleep mode. 7.14 internal voltage reference the internal voltage reference is an accurate 0.9 v and is the output of a low voltage band gap circuit. a typical value at t amb = 25 ? c is 0.903 v. this value varies typically only ? 3 mv over the 0 ? c to 85 ? c temperature range (see ta b l e 2 1 and figure 21 ). 7.15 general-purpose externa l event counter/timers the em783 includes one 32-bit counter/timer and one 16-bit counter/timer. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? four capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. up to three capture channels are pinned out. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.16 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.17 windowed watc hdog timer (wwdt) if software fails to service th e controller periodically with in a programmable time window, the purpose of the watchdog is to reset it.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 20 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.17.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time before a watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? if enabled, an incorrect feed sequence causes a reset or interrupt. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the in ternal rc oscillator (irc), or the dedicated watchdog oscilla tor (wdosc). this gives a wide range of potential timing choices of watchdog oper ation under different power conditions. 7.18 clocking and power control 7.18.1 crystal and internal oscillators the em783 includ e four in dependent oscillators. 1. the crystal oscillator (syso sc) operating at frequencie s between 1 mhz and 25 mhz. 2. the internal rc oscillator (irc) with a fi xed frequency of 12 mhz, trimmed to 1 % accuracy. 3. the internal low-power, low-frequency oscillator (lfosc) with a programmable nominal frequency between 9.4 kh z and 2.3 mhz with 40 % accuracy. 4. the dedicated watchdog oscillator (wdosc) with a programmable nominal frequency between 9.4 khz and 2.3 mhz with 40 % accuracy. each oscillator, except the wdosc, can be used for more than one purpose as required in a particular application. following reset, the em783 operates from the irc until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 4 for an overview of the em783 clock generation.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 21 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.18.1.1 internal rc oscillator (irc) the irc may be used as the clock source for the wwdt, and/or as the clock that drives the pll and subsequently the cpu. the nomi nal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the irc can be used as a clock source fo r the cpu with or without using the pll. the irc frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. upon power-up or any chip reset, the em783 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.18.1.2 crystal oscillator (sysosc) the crystal oscillator can be used as the clo ck source for the cpu, with or without using the pll. the sysosc operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 4. em783 clock generation block diagram aaa-009615 system pll irc sysosc wdosc irc lfosc mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider system sysclkctrl[1:18] memories and peripherals ssp0 peripheral clock divider ssp0 usart peripheral clock divider usart wwdt clock divider wwdt wdclksel lfosc irc sysosc clkout pin clock divider clkout pin clkoutuen (clkout update enable) main clock system clock irc 18 clkin
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 22 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.18.1.3 internal low-frequency oscillator (lfosc) and watchdog oscillator (wdosc) the lfosc and the wdosc are identical inter nal oscillators. the nom inal frequency is programmable betwee n 9.4 khz and 2.3 mhz. the frequency spread over silicon process variations is ? 40 %. the wdosc is a dedicated oscillator for the windowed wwdt. the lfosc can be used as a clock source that directly drives th e cpu or the clkout pin. 7.18.2 clock input a 3.3 v external clock source (25 mhz typical) can be supplied on the selected clkin pin. a 1.8 v external clock source can be supplied on the xtalin pin (see section 12.1 ). 7.18.3 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz. there is an additional di vider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insu red that the pll output has a 50 % duty cycle. software can enable the pll and it is turned off and bypassed following a chip reset. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.18.4 clock output the em783 features a clock output function th at routes the irc, the sysosc, the lfosc, or the main clock to an output pin. 7.18.5 wake-up process the em783 begin operation at power-up and when awakened from deep power-down mode by using the irc as the clock source. this allows chip operation to resume quickly. if the application requires the sysosc, the external clock source, or the pll, software must enable these features. before using them as a clock source, wait for them to stabilize. 7.18.6 power control the em783 supports the arm cortex-m0 slee p mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. th is control allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip periphe rals. the clock control allows fine-tuning of power consumption. it eliminates all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control. 7.18.6.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 23 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.18.6.2 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the em783 for one of the following power modes: ? power mode 0: default mode corresponding to power configuration after reset. ? power mode 1: cpu performance mode corresponding to optimized processing capability. ? power mode 2: efficiency mode correspo nding to optimized balance of current consumption and cpu performance. ? power mode 3: low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 7.19 system control 7.19.1 undervoltage lockout (uvlo) protection see section 10.1 ? power supply fluctuations ? for details on the settling times of the bod and por circuits. these circuits constitute the uvlo protection. 7.19.2 reset reset has four sources on the em783: the reset pin, the watchdog reset, power-on reset (por), the arm sysresetreq software request and the br ownout detection (bod) circuit. the reset pin is a schmitt trigger input pin and uses a special pad (see figure 25 ). assertion of chip reset by any source (after the operating voltage attains a usable level) starts the irc and initializes the flash controller. after the bod and the por resets are released, the internal reset timer counts for 100 ? s until the internal reset is removed. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. writing to a special function register allows th e software to reset pe ripherals such as the i 2 c-bus interface, usart, ssp cont roller, counter/timers and dac.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 24 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.19.3 brownout detection the em783 includes two programmable levels for monitoring the voltage on the v dd(3v3) pin. if this voltage falls below one of the fo ur selected levels, the bod asserts an interrupt signal to the nvic. to cause a cpu interrupt, this signal is enabled for interrupt in the interrupt enable register in the nvic. software can monitor the signal by reading a dedicated status register. in addition, the bod circuit supports one hardware controlled voltage level for triggering a chip reset. 7.19.4 code security (code read protection - crp) this feature of the em783, allows different levels of security to be enabled in the system. it is used to restrict access to the on-chip flash and use of the serial wire debugger (swd) and in-system-programming (isp). when needed, crp is invoked by programming a specific pattern into a dedicat ed flash location. the crp does not affect iap commands. in addition, isp entry via the p0_1 pin can be disabled without enabling crp. refer to the em783 user manual for specific details. there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode ef fectively disables isp override using p0_1 pin. to enable flash update via the usart, the user application must provide a flash update mechanism using iap calls or call reinvoke isp command. in addition to the three crp levels, sampling of pin p0_1 for valid user code can be disabled. refer to the em783 user manual for specific details. 7.19.5 apb interface the apb peripherals are located on one apb bus. 7.19.6 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the boot rom. 7.19.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 25 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 7.20 emulation and debugging debug functions are integrated into the arm cortex-m0. serial wire debug (swd) with four breakpoints and two watchpoints is supported. 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise specified. all voltages relate to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 6) and below ground that can be applied for a short t ime (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins except true open-drain pins p0_2 and p0_3 and except the 3 v tolerant pins p0_4 and p0_ 5. [4] including the voltage on outputs in 3-state mode. [5] v dd(io) present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd(io) is powered down. [6] applies to 3 v tolerant pins p0_4 and p0_5. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) [2] ? 0.5 +4.6 v v dd(io) input/output supply voltage [2] ? 0.5 +4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(io) supply voltage is present [2] [3] [4] ? 0.5 +5.5 v on pins p0_2 and p0_3 [5] ? 0.5 +5.5 v 3 v tolerant i/o pins without over-voltage protection [6] ? 0.5 v dd(io) v metrology [7] ? 0.5 +4.6 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ? c - 100 ma t stg storage temperature [8] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [9] ? 6500 +6500 v
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 26 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [7] a metrology engine input voltage above 3.6 v can be applied for a short time without leading to immediate, unrecoverable fai lure. accumulated exposure to elevated voltages at 4.6 v must be less than 10^6 s total over the lifetime of the device. applying an elevated voltage to the metrology engine inputs for a long time affect s the reliability of the devic e and reduces its lifetime. [8] dependent on package type. [9] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 9. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) 2.6 3.3 3.6 v v dd(io) input/output supply voltage 2.6 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash; v dd(3v3) = v dd(io) = 3.3 v; low-current mode (see section 7.18.6.2 ) system clock = 12 mhz; all peripherals disabled [2] [4] [5] -3-m a system clock = 48 mhz; all peripherals disabled [2] [6] [5] -8-m a sleep mode; system clock = 12 mhz; v dd(3v3) = v dd(io) = 3.3 v; power mode 0 (see section 7.18.6.2 ) all peripherals disabled; 12 mhz [2] [4] [5] -2-m a all peripherals disabled; 48 mhz [2] [4] [5] -5-m a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 1000 na i ih high-level input current v i =v dd(io) ; on-chip pull-down resistor disabled - 0.5 1000 na i oz off-state output current v o =0v; v o =v dd(io) ; on-chip pull-up/down resistors disabled - 0.5 1000 na v i input voltage pin configured to provide a digital function 5 v tolerant pins [7] [8] 0- 5 . 0v 3 v tolerant pins: p0_4 and p0_5 [7] [8] v dd(io) v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 27 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom v il low-level input voltage - - 0.3v dd(io) v v hys hysteresis voltage 3.0 v ? v dd(io) ?? 3.6 v 0.4 - - v v oh high-level output voltage 2.6 v ? v dd(io) ?? 3.6 v; i oh = ? 4 ma 0.85v dd(io) --v v ol low-level output voltage 2.6 v ? v dd(io) ?? 3.6 v; i ol =4 ma --0.15v dd(io) v i oh high-level output current v oh =v dd(io) ? 0.4 v; 2.6 v ? v dd(io) ?? 3.6 v ? 4--ma i ol low-level output current v ol =0.4v 2.6 v ? v dd(io) ?? 3.6 v 4--m a i ohs high-level short-circuit output current v oh =0v [9] --? 45 ma i ols low-level short-circuit output current v ol =v dd(io) [9] --5 0m a i pd pull-down current v i =5v [10] 10 50 150 ? a i pu pull-up current v i =0v; 2.6 v ? v dd(io) ?? 3.6 v ? 15 ? 50 ? 85 ? a v dd(io) em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 28 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; sysosc disabled; system pll disabled. [5] all digital peripherals disabled in the sysclkctrl register except rom, ram, and flash. peripheral clocks to usart and ssp0/ 1 disabled in system configuration block. analog peripherals disabled in the p druncfg register except flash memory. [6] irc disabled; sysosc enabled; system pll enabled. [7] including voltage on outputs in 3-state mode. [8] all supply voltages must be present. [9] allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] does not apply to 3 v tolerant pins p0_4. [11] to v ss . i ol low-level output current v ol =0.4v 2.6 v ? v dd(io) ?? 3.6 v 4--m a i ohs high-level short-circuit output current v oh =0v [9] --? 160 ma i ols low-level short-circuit output current v ol =v dd(io) [9] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v 2.6 v ? v dd(io) ?? 3.6 v ? 15 ? 50 ? 85 ? a v dd(io) em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 29 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 9.1 power consumption power measurements in active and sleep modes were performed under the following conditions (see em783 user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpion dir registers. ? drive all gpio outputs to low. conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; all analog peripherals disabled in the pdruncfg register; power mode 0 (see section 7.18.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 5. active mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) 002aah184 -40 -15 10 35 60 85 0 1.6 3.2 4.8 6.4 8 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 30 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals enabled in the sysahbclkctrl register; all analog peripherals enabled in the pdruncfg register; power mode 0 (see section 7.18.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 6. active mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals enabled) conditions: v dd(3v3) = 3.3 v; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register and pdruncfg register ; all peripheral cloc ks disabled; bod disabled; power mode 0 (see section 7.18.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 7. sleep mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) 002aah185 2.7 3 3.3 3.6 0 1.6 3.2 4.8 6.4 8 v dd(3v3) (v) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aah186 -40 -15 10 35 60 85 0 1.6 3.2 4.8 6.4 8 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 31 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 9.2 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. [1] irc on; pll off. 9.3 electrical pi n characteristics table 7. power consumption for individual analog and digital blocks peripheral typical supply current in ma average ? a/mhz 12 mhz [1] analog peripherals bod 0.05 - metrology engine 0.10 - dac 0.26 - digital peripherals usart 0.15 12 i2c 0.02 2 16-bit counter/timer 0 0.02 2 32-bit counter/timer 0 0.02 2 wwdt 0.02 2 conditions: v dd(io) = 3.3 v; on pin p0_21. fig 8. high-current source output driver: typical high-level output voltage v oh versus high-level output current i oh i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 32 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom conditions: v dd(io) = 3.3 v; on pins p0_2 and p0_3. fig 9. high-current sink pins: typical low-level output current i ol versus low-level output voltage v ol conditions: v dd(io) = 3.3 v; standard port pins and p0_21. fig 10. typical low-l evel output current i ol versus low-level output voltage v ol v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 33 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom conditions: v dd(io) = 3.3 v; standard port pins. fig 11. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(io) = 3.3 v; standard port pins. fig 12. typical pull-up current i pu versus input voltage v i i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 34 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom conditions: v dd(io) = 3.3 v; standard port pins. fig 13. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 35 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 10. dynamic characteristics 10.1 power supply fluctuations if the input voltage (v dd(3v3) ) to the internal regulator fluctuates, the em783 is held in reset during a brownout condition as long as the uvlo circuit is operating. the settling times of the bod and por circuits, which co nstitute the uvlo, determine the minimum time the supply level must remain in the shallow or deep brownout condition. this time ensures that the internal reset is asserted properly. 10.2 power supply voltage profile the use of power supply ramp-up and ramp-dow n procedures outside of the specification shown in ta b l e 9 results in functional failure of the em783. table 8. por and bod circui t settling characteristics symbol parameter conditions min typ max unit t s settling time power droop: from active level to shallow brownout level (0.9 v ? v dd(3v3) ? 2.4 v) 5-- ? s from active level to deep brownout level (0 v < v dd(3v3) < 0.9 v) 12 - - ? s fig 14. uvlo timing external power supply bod trip point (typical) por trip point (typical) internal reset time brown-out shallow brown-out deep supply voltage v dd(3v3) 2.4 v 0.9 v 0 v cold start-up > 5 s > 12 s 002aah326
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 36 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] values are derived from simulation. table 9. power supply ramp characteristics t amb = ?40 ? c to 85 ?? c. [1] symbol parameter conditions min typ max unit cold power-up (see regions a to c in figure 15 ) t wait wait time region a : power-down supply voltage = gnd [1] --- - t r rise time region b : ramp up gnd ? supply voltage ? v dd 0- - ? s t wait wait time region c : powered-up supply voltage = v dd 150 - - ? s shallow power droop cycle (see regions d to g in figure 15 ); bod enabled t f fall time region d : ramp down v dd ? supply voltage > v th(fast_ramp) 0- - ? s t wait wait time region e : power-down v th(fast_ramp) ? supply voltage < v th(uvlo) 5- - ? s t r rise time region f : ramp up v th(fast_ramp) ? supply voltage < v dd 0- - ? s t wait wait time region g : powered-up supply voltage = v dd 5- - ? s deep power droop cycle (see regions h to j in figure 15 ) t wait wait time region h : power-down gnd < supply voltage < v th(fast_ramp) 12 - - ? s t r rise time region i : ramp up gnd ? supply voltage < v dd 0- - ? s t wait wait time region j : powered-up supply voltage = v dd 150 - - ? s voltage thresholds v th(droop) droop threshold voltage - 900 - mv
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 37 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom fig 15. power supply voltage profile ab: t r f: t r g: t wait c: t wait e: t wait d: t f h: t wait j: t wait i: t r gnd v th(droop) = 300 mv v dd bod reset level supply voltage on pin v dd regions d - g (shallow power droop cycle) regions h - j (deep power droop cycle) regions a - c (cold power up) aaa-009616
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 38 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 10.3 flash/eeprom memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes to the flash. data must be written to the flash in blocks of 256 bytes. flash programming is accomplished via iap calls (see em783 user manual ). execution time of iap calls depends on the system clock and is ty pically between 1.5 ms and 2 ms per 256 bytes. 10.4 external clock for o scillator in slave mode remark: the input voltage on the xtalin pin must be ? 1.95 v (see ta b l e 6 ). for connecting the oscillator to the xtalin/xtalout pins, see section 12.1 . [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 10. flash characteristics t amb = ? 40 ? c to +85 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 20 - years unpowered 20 40 - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 11. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd(3v3) = 2.6 v to 3.6 v. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance 100000 1000000 - cycles t ret retention time powered 100 200 - years unpowered 150 300 - years t er erase time 64 bytes - 1.8 - ms t prog programming time 64 bytes - 1.1 - ms table 12. dynamic characteristic: ext ernal clock (xtalin or clkin pin) t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 39 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 10.5 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. fig 16. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 13. dynamic characteristic: irc t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd(3v3) ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 17. internal irc frequency vs. temperature table 14. dynamic characteri stics: wdosc and lfosc symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz aaa-009888 11.95 12.05 12.15 f (mhz) 11.85 temperature (c) -40 85 35 10 60 -15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 40 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the em783 user manual . 10.6 i/o pins [1] applies to standard port pins and reset pin. simulated results. [2] sso indicates maximum number of simultaneously swit ching digital output pins. the pins are optimized for half of the maximum sso. [3] set slew bit in the ioconfig register to 1. [4] set slew bit in the ioconfig register to 0. 10.7 i 2 c-bus remark: all i 2 c modes (standard-mode, fast-mode, fa st-mode plus) can be configured for the true open-drain pins p0_2 and p0_3. if the limited-performance i 2 c-bus pins are used (i 2 c-bus functions on standard i/o pins), only standard-mode with internal pull-up enabled or fast-mode with external pull-up resistor are supported. table 15. dynamic characte ristic: digital i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd(io) ? 3.6 v; load capacitor = 30 pf. symbol parameter conditions min typ max unit t r rise time pin configured as output sso = 1 [2] [3] 2.5 - 5.0 ns sso = 6 [2] [3] 2.5 - 4.5 ns sso = 16 [2] [4] 3.0 - 5.0 ns t f fall time pin configured as output sso = 1 [2] [3] 2.0 - 4.5 ns sso = 6 [2] [3] 2.0 - 4.5 ns sso = 16 [2] [4] 2.5 - 5.0 ns table 16. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 41 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowledge. [4] a device must provide an internal hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal). the hold time is to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat can be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with res pect to the rising edge of scl. it applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns before the scl line is released. this is in accordance with the standard-mode i 2 c-bus specification. also the a cknowledge timing must meet this set-up time. t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns table 16. dynamic characteristic: i 2 c-bus pins [1] ?continued t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit fig 18. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 42 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 10.8 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time derived from the ssp bit rate t cy(clk) , is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 register) and the ssp cpsdvsr parameter (specified in the ssp clock prescale register). [2] t amb = ?40 ? c to +85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd(3v3) = 3.3 v. table 17. dynamic ch aracteristics of ssp pins in spi mode 2.6 v <= vdd(3v3) = vdd(io) <= 3.6 v. symbol parameter conditions min typ max unit ssp master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 - - ns t ds data set-up time in spi mode [2] 15 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s ssp slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 43 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom pin names sck, miso, and mosi refer to pins for ssp peripheral ssp0. fig 19. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 aaa-009617
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 44 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 11. characteristics of analog peripherals [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see em783 user manual . pin names sck, miso, and mosi refer to pins for ssp peripheral ssp0. fig 20. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 aaa-009618 table 18. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 45 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom [1] measured on typical samples. [1] characterized through simulation. [2] characterized on a typical silicon sample. [3] measured over process variations. table 19. dac static and dy namic characteristics v dd(3v3) = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error -- ? 1lsb e l(adj) integral non-linearity -- ? 2lsb e o offset error - - 25 mv e g gain error - - 25 mv c l load capacitance - - 200 pf r l load resistance 1 - - k ? r o output resistance [1] -< 40 ? f c(dac) dac conversion frequency -0.41mhz t s settling time - - 1 ? s v o output voltage output voltage range with less than 1 lsb deviation; with minimum r l connected to ground or power supply 0.3 - v dd(3v3) ? 0.3 v with minimum r l connected to ground or power supply 0.175 - v dd(3v3) ? 0.175 v table 20. dac sampling frequency range and power consumption bias bit maximum current dac sampling frequency range 0700 ? a 0 mhz to 1 mhz 1350 ? a 0 mhz to 400 khz table 21. internal voltage reference static and dynamic characteristics symbol parameter conditions min typ max unit v o output voltage t amb = ? 40 ? c to +85 ?c [1] 0.855 0.900 0.945 v t amb = 70 ? c to +85 ?c [2] -0.906- v t amb = 50 ?c [2] -0.905- v t amb = 25 ?c [3] 0.893 0.903 0.913 v t amb = 0 ?c [2] -0.902- v t amb = ? 20 ?c [2] -0.899- v t amb = ? 40 ?c [2] -0.896- v t s(pu) power-up settling time up to 90 % of v o [3] - 144 195 ? s
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 46 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom v dd(3v3) = 3.3 v fig 21. typical internal voltage reference output voltage 002aag063 temperature (c) -40 85 35 10 60 -15 895 905 900 910 v o (mv) 890
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 47 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 12. application information 12.1 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if a clock in slave mode drives the oscillator, it is recommended that the input is coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode, the input clock signal should be coupled using a capacitor of 100 pf ( figure 22 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 23 and in ta b l e 2 2 and table 23 . since the feedback resistance is integrated on chip, for fundamental mode os cillation, only connect a crystal and the capacitances c x1 and c x2 externally. l, c l and r s define the fundamental frequency. capacitance c p in figure 23 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see table 22 ). fig 22. slave mode operation of the on-chip oscillator fig 23. oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation aaa-009613 emxxx c g c i 100 pf xtalin aaa-009614 emxxx xtalout xtal = c x2 r s l c l c p c x1 xtalin
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 48 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 12.2 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. to keep the noise coupled in via the pcb as small as possible, loops must be made as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen to accommodate the increase in parasitics of the pcb layout. 12.3 standard i/o pad configuration figure 24 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with co nfigurable open-drain output ? digital input: weak pull-up resistor (pmos device) enabled/disabled ? digital input: weak pull-down resistor (nmos device) enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input glitch f ilter selectable on 17 pins ? analog input table 22. recommended values for c x1 /c x2 in oscillation mode (low frequency mode) fundamental oscillation frequency f osc xtal load capacitance c l max. xtal series resistance r s external load capacitors c x1 c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf 18 pf 20 pf < 300 ? 39 pf 39 pf 30 pf < 300 ? 57 pf 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf 18 pf 20 pf < 200 ? 39 pf 39 pf 30 pf < 100 ? 57 pf 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf 18 pf 20 pf < 60 ? 39 pf 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf 18 pf table 23. recommended values for c x1 /c x2 in oscillation mode (high frequency mode) fundamental oscillation frequency f osc xtal load capacitance c l max. xtal series resistance r s external load capacitors c x1 c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf 18 pf 20 pf < 100 ? 39 pf 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf 18 pf 20 pf < 80 ? 39 pf 39 pf
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 49 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 12.4 reset pad configuration fig 24. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter remark: the internal pull-up r pu is disconnected in deep-power down mode. to prevent the reset pin from floating in deep power-down mode, an external pull-up resistor should be added. fig 25. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 50 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 12.5 uvlo protection and reset timer circuit 12.6 guidelines for selecting a power s upply filter for uvlo protection for the uvlo circuits to hold the part in reset during shallow and deep brownout conditions, the power supply line must be filt ered to allow the bod and por circuits to settle when short voltage drops occur (see section 10.1 ? power supply fluctuations ? ). select the capacitance of the decoupling/by pass capacitor in a ccordance with the following guidelines. c >> i dd ? t s / ? v dd(3v3) with: ? ? v dd(3v3) ? 100 mv for a voltage drop below the bod and por trip points. ? i dd ? 3 ma with the irc running and pll/sysosc off (see figure 6 ). ? t s = 5 ? s for shallow brownout (see table 8 ). ? t s = 12 ? s for deep brownout (see ta b l e 8 ). with these parameters, the value of the decoupling/bypass capacitor to be added to the supply line is: ? c = 0.15 ? f for shallow brownout. ? c = 0.36 ? f for deep brownout. fig 26. functional diagram of the uvlo protection and reset timer circuit 002aah324 internal regulator v int 1.8 v v ext v int v int analog reset v ref por v ext 3.3 v uvlo bod por or or external reset internal reset 100 s reset timer
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 51 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 13. package outline fig 27. package outline hvqfn33 references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 52 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 14. soldering fig 28. reflow soldering of the hvqfn33(7x7) package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 53 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 15. abbreviations 16. revision history table 24. abbreviations acronym description ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection gpio general purpose input/output i 2 c inter-integrated circuit jedec joint electron devices engineering council nvm non-volatile memory pll phase-locked loop spi serial peripheral interface ssi serial synchronous interface ttl transistor-transistor logic usart universal synchronous/asynchronous receiver/transmitter uvlo under-voltage lockout table 25. revision history document id release date data sheet status change notice supersedes em783 v.2 20140117 product data sheet - em783 v.1 em783 v.1 20131108 objective data sheet - -
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 54 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 55 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 56 of 58 nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 19. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . .3 table 3. pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . .5 table 4. em783 pin description . . . . . . . . . . . . . . . . . . .8 table 5. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .25 table 6. static characteristics . . . . . . . . . . . . . . . . . . . .26 table 7. power consumption for individual analog and digital blocks . . . . . . . . . . . . . . . . . . . . . . .31 table 8. por and bod circuit settling characteristics . .35 table 9. power supply ramp char acteristics . . . . . . . . .36 table 10. flash characteristics . . . . . . . . . . . . . . . . . . . . .38 table 11. eeprom characteristics . . . . . . . . . . . . . . . . .38 table 12. dynamic characteristic: external clock (xtalin or clkin pin) . . . . . . . . . . . . . . . . . .38 table 13. dynamic characteristic: irc . . . . . . . . . . . . . . .39 table 14. dynamic characteristics: wdosc and lfosc. .39 table 15. dynamic characteristic: digital i/o pins [1] . . . . . 40 table 16. dynamic characteristic: i 2 c-bus pins [1] . . . . . . 40 table 17. dynamic characteristics of ssp pins in spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. bod static characteristics [1] . . . . . . . . . . . . . . . 44 table 19. dac static and dynamic characteristics . . . . . 45 table 20. dac sampling frequency range and power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21. internal voltage reference static and dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 22. recommended values for c x1 /c x2 in oscillation mode (low frequency mode) . . . . . . . . . . . . . . 48 table 23. recommended values for c x1 /c x2 in oscillation mode (high frequency mode) . . . . . . . . . . . . . . 48 table 24. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 25. revision history . . . . . . . . . . . . . . . . . . . . . . . . 53 20. figures fig 1. em783 block diagram . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin configuration hvqfn33 package . . . . . . . . . .5 fig 3. em783 memory map . . . . . . . . . . . . . . . . . . . . . .14 fig 4. em783 clock generation block diagram . . . . . . . .21 fig 5. active mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) . . . . . . . . . . . . . . . . . . .29 fig 6. active mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals enabled) . . . . . . . . . . . . . . . . . . .30 fig 7. sleep mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) . . . . . . . . . . . . . . . . . . .30 fig 8. high-current source output driver: typical high-level output voltage v oh versus high-level output current i oh . . . . . . . . . . . . . . .31 fig 9. high-current sink pins : typical low-level output current i ol versus low-level output voltage v ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 fig 10. typical low-level output current i ol versus low-level output voltage v ol . . . . . . . . . . . . . . .32 fig 11. typical high-level output voltage v oh versus high-level output source current i oh . . . . . . . . .33 fig 12. typical pull-up current i pu versus input voltage v i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 fig 13. typical pull-down current i pd versus input voltage v i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 14. uvlo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 fig 15. power supply voltage profile . . . . . . . . . . . . . . . .37 fig 16. external clock timing (with an amplitude of at least v i(rms) = 200 mv) . . . . . . . . . . . . . . . .39 fig 17. internal irc frequency vs. temperature . . . . . . . .39 fig 18. i 2 c-bus pins clock timing . . . . . . . . . . . . . . . . . . .41 fig 19. ssp master timing in spi mode. . . . . . . . . . . . . .43 fig 20. ssp slave timing in spi mode . . . . . . . . . . . . . . .44 fig 21. typical internal voltage reference output voltage.46 fig 22. slave mode operation of the on-chip oscillator . . 47 fig 23. oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation . . . . . . . . . . . 47 fig 24. standard i/o pad configuration . . . . . . . . . . . . . . 49 fig 25. reset pad configuration . . . . . . . . . . . . . . . . . . . 49 fig 26. functional diagram of the uvlo protection and reset timer circuit. . . . . . . . . . . . . . . . . . . . . . . . . 50 fig 27. package outline hvqfn33 . . . . . . . . . . . . . . . . . 51 fig 28. reflow soldering of the hvqfn33(7x7) package 52
em783 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 17 january 2014 57 of 58 continued >> nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . 13 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 13 7.2 on-chip flash program memo ry . . . . . . . . . . . 13 7.3 on-chip eeprom data memory. . . . . . . . . . . 13 7.4 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.6 nested vectored interrupt controller (nvic) . 14 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15 7.7 ioconfig block . . . . . . . . . . . . . . . . . . . . . . 15 7.8 fast general-purpose parallel i/o . . . . . . . . . . 15 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.9 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10 ssp serial i/o controller . . . . . . . . . . . . . . . . . 16 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.11 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 17 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 metrology engine . . . . . . . . . . . . . . . . . . . . . . 17 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.13 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.14 internal voltage reference . . . . . . . . . . . . . . . . 19 7.15 general-purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16 system tick timer . . . . . . . . . . . . . . . . . . . . . . 19 7.17 windowed watchdog timer (wwdt) . . . . . . 19 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.18 clocking and power control . . . . . . . . . . . . . . 20 7.18.1 crystal and internal oscillators . . . . . . . . . . . . 20 7.18.1.1 internal rc oscillator (irc) . . . . . . . . . . . . . . 21 7.18.1.2 crystal oscillator (sysosc). . . . . . . . . . . . . . . 21 7.18.1.3 internal low-frequency oscillator (lfosc) and watchdog oscillator (wdosc) . . . . . . . . . . . . 22 7.18.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18.3 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18.4 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18.5 wake-up process . . . . . . . . . . . . . . . . . . . . . . 22 7.18.6 power control . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18.6.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18.6.2 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19 system control . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19.1 undervoltage lockout (uvlo) protection . . . 23 7.19.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19.3 brownout detection . . . . . . . . . . . . . . . . . . . . 24 7.19.4 code security (code read protection - crp) 24 7.19.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.19.6 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.19.7 external interr upt inputs . . . . . . . . . . . . . . . . . 24 7.20 emulation and debugging . . . . . . . . . . . . . . . 25 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 9 static characteristics . . . . . . . . . . . . . . . . . . . 26 9.1 power consumption . . . . . . . . . . . . . . . . . . . 29 9.2 peripheral power consumption . . . . . . . . . . . 31 9.3 electrical pin characteristics. . . . . . . . . . . . . . 31 10 dynamic characteristics. . . . . . . . . . . . . . . . . 35 10.1 power supply fluctuations . . . . . . . . . . . . . . . 35 10.2 power supply voltage profile . . . . . . . . . . . . . 35 10.3 flash/eeprom memory . . . . . . . . . . . . . . . . 38 10.4 external clock for oscillator in slave mode . . . 38 10.5 internal oscillators . . . . . . . . . . . . . . . . . . . . . 39 10.6 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.7 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.8 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 characteristics of analog peripherals. . . . . . 44 12 application information . . . . . . . . . . . . . . . . . 47 12.1 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.2 xtal printed-circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.3 standard i/o pad configuration . . . . . . . . . . . 48 12.4 reset pad configuration . . . . . . . . . . . . . . . . . 49 12.5 uvlo protection and rese t timer circuit . . . . . 50 12.6 guidelines for selecting a power supply filter for uvlo protection . . . . . . . . . . . . . . . . . . . . . . 50 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 51 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 53 17 legal information . . . . . . . . . . . . . . . . . . . . . . 54 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 54 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 55
nxp semiconductors em783 energy metering ic; 32 kb flash, 8 kb sram, 4 kb eeprom ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 january 2014 document identifier: em783 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18 contact information. . . . . . . . . . . . . . . . . . . . . 55 19 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 20 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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